Huajin Securities released a research report saying that according to the data of the semiconductor Chuangxin network, the price of TSMC's 3nm and 5nm process technology will rise by 5% to 10%, and the price of CoWoS process will increase by 15% to 20% (short supply), which is not only due to the surge in demand for computing power in the AI field, but also shows the rising cost of process technology. The CoWoS-L interposer consists of multiple local silicon interconnect (LSI) chips and a global redistribution layer (RDL) to form a recombinant interposer (RI) to replace the monolithic silicon interposer in CoWoS-S. CoWoS-L has successfully implemented a connector with 3 times the mask size (about 2500 square millimeters), equipped with multiple SoCs/chip modules and 8 HBM solutions.

The main views of Huajin Securities are as follows:

Event: According to Taiwanese media "Liberty Finance", TSMC will increase the foundry price of its 3nm, 5nm and CoWoS processes from January 2025, and the increase is expected to be between 5% and 20%.

CoWoS may usher in a rise in volume/price/demand, and the trend of CoWoS-S turning to CoWoS-L is obvious

Volume: According to DIGITIMESResearch, the global demand for CoWoS and similar packaging capacity could increase by 113% in 2025, driven by strong demand for cloud-based AI accelerators. Major suppliers TSMC, ASE Technology Holdings (including Silicon Precision Industries, SPIL) and Amkor are expanding production capacity.

According to the DIGITIMESResearch report, by the end of the fourth quarter of 2025, TSMC's monthly production capacity is expected to increase to more than 65,000 pieces of 12-inch wafer equivalent, while the production capacity of Amkor and ASE Photosynthesis will increase to 17,000 wafers, NVIDIA is TSMC's largest customer of CoWoS packaging process, benefiting from the mass production of NVIDIA Blackwell series GPUs, TSMC will switch from CoWoS-S to CoWoS-L process from the fourth quarter of 2025, making CoWoS-L the main process of TSMC's CoWoS technology, and NVIDIA's demand for CoWoS-L process may increase significantly from 32,000 wafers in 2024 to 380,000 wafers in 2025, a year-on-year increase of 1018%. According to DIGITIMESResearch, CoWoS-L will account for 54.6% of TSMC's total CoWoS production capacity in the fourth quarter of 2025, while CoWoS-S will account for 38.5% and CoWoS-R will be 6.9%.

Price: According to the data of Semiconductor Chuangxin.com, the price of TSMC's 3nm and 5nm process technology will rise by 5% to 10%, and the price of CoWoS process will increase by 15% to 20% (short supply), which is not only due to the surge in demand for computing power in the AI field, but also shows the rising cost of process technology.

Demand: According to semiconductor data, NVIDIA accounts for more than 50% of the overall supply of CoWoS, A100, H100 and Blackwell Ultra and other products will use CoWoS packaging, and in 2025, NVIDIA will promote the B300 and GB300 series with CoWoS-L technology. AMD's MI300 is available in TSMC SoIC (3D) and CoWoS (2.5D) package technologies. In addition, Broadcom, Microsoft, Amazon, and Google also have certain needs for CoWoS.

CoWoS-L ensures good system performance while avoiding yield loss for large silicon interposers

The CoWoS-L interposer consists of multiple local silicon interconnect (LSI) chips and a global redistribution layer (RDL) to form a recombinant interposer (RI) to replace the monolithic silicon interposer in CoWoS-S. LSIChiplet retains sub-micron copper interconnects, through-silicon vias (TSVs), and embedded deep trench capacitors (eDTCs) compared to CoWoS-S to ensure good system performance while avoiding large silicon interposer yield loss issues. In addition, through insulator vias (TIV) are introduced in RI as a vertical interconnect to provide a lower insertion loss path than TSV.

CoWoS-L has successfully implemented a connector with 3 times the mask size (about 2500 square millimeters), equipped with multiple SoCs/chip modules and 8 HBM solutions. There are two routes of LSI fabrication, LSI-1 and LSI-2, with the main difference being the interconnect metal scheme:

1) In the manufacture of LSI-1, TSV and a single layer of Damascus copper metal (M1) are first fabricated on a 300 mm silicon chip. Then, an interconnect structure is formed with double Damascus copper with undoped silicate glass (USG) as the dielectric layer. In the LSI-1 metal solution, the double Damascus copper process provides a minimum metal width/space of 0.8/0.8 μm and a thickness of 2 μm. 2) LSI-2 has the same TSV structure and M1 metal scheme. After the M1 layer is fabricated, the copper RDL with polyimide (PI) as the dielectric layer is formed into an interconnected structure through the semi-new process (SAP). SAP copper RDL has a minimum width/space of 2/2 μm and a thickness of 2.3 μm.

Investment advice

Huajin Securities believes that the current ChatGPT relies on large models, big data, and large computing power support, and its emergence marks the starting point of general artificial intelligence and the inflection point of strong artificial intelligence, and the future computing power will lead the next digital revolution, and the demand for high-end chips such as xPU continues to grow. As the concept of chiplet packaging continues to advance, the industry chain of advanced packaging (packaging and testing/equipment/materials/IP, etc.) will continue to benefit.

It is advisable to pay attention to the target

Packaging and testing: Tongfu Microelectronics (002156.SZ), Changdian Technology (600584.SH), Huatian Technology (002185.SZ), Yongsi Electronics (688362.SH), Weice Technology (688372.SH).

Equipment: North Huachuang (002371.SZ), China Micro Corporation (688012.SH), Shengmei Shanghai (688082.SH), Huafeng Measurement and Control (688200.SH), Changchuan Technology (300604.SZ), Zhongke Flying Measurement (688361.SH), Huahai Qingke (688120.SH).

Materials: Huahai Chengke (688535.SH), Dinglong (300054.SZ), Shennan Circuit (002916.SZ), Xingsen Technology (002436.SZ), Shanghai Xinyang (300236.SZ), Novoray New Materials (688300.SH), Feikai Materials (300398.SZ).

EDA: Empyrean (301269.SZ), Guangli Micro (301095.SZ), Primarius (688206.SH).

IP: VeriSilicon (688521.SH).

Risk Warning

Lower-than-expected recovery in downstream demand; The research and development of advanced packaging technology is less than expected; Artificial intelligence is not developing as expected; Systemic risk.